Much of recent technological progress embraces the increasing miniaturization afforded by advances in integrated circuit processing technology. Dramatic improvements in the circuit density available on individual integrated circuit chips have been made. Typically, integrated circuit chips are individually packaged and the packages are mounted on printed circuit boards. The sizes of the packages limit chip density on the printed circuit board, requiring larger systems and limiting overall circuit performance due to longer inter-chip connections.
More recently, multi-chip carriers have been developed which permit multiple integrated circuit chips to be mounted on a common carrier without the need for packaging the individual chips. This allows the chips to be packed more closely together.
While multi-chip carriers have been fabricated using a variety of technologies, the greatest chip density has been achieved by multi-chip carriers fabricated using integrated circuit processing technology. In other words, a multi-chip carrier can be fabricated by photolithographically defining multiple layers of circuits interconnected by metal vias through intermediate dielectric layers. Individual integrated circuit chips attach to the upper layer of the multi-chip carrier and receive and transmit electrical signals through the multi-chip carrier's circuit layers and vias.
The vias which carry electrical signals from one circuit layer to another are typically formed as follows. Apertures are photolithographically defined in a dielectric layer deposited over a lower circuit layer. Copper vias are then formed in these apertures by sputtering or by chemical vapor deposition. Copper is the preferred via material because of its excellent conductivity and current-carrying capacity; however copper does not bond effectively with dielectrics and requires a distinct adhesive layer, e.g., chromium, to bond the copper to the dielectric. Aluminum bonds readily with dielectrics without an intermediate adhesion layer, and for this reason is also sometimes used.
The vias formed by conventional sputtering or chemical vapor deposition are hollow. Hollow vias cannot be stacked through successive layers because of attendant photolithographic difficulties. Specifically, a photoresist layer follows the curvature of the hollow via's surface. The resulting curvature causes deviations in the collimated light beam used to define patterns in the photoresist; these deviations prevent certain regions of the photoresist from being exposed, and conversely, expose other regions that must not be exposed, so that the desired pattern for the next circuit layer cannot be formed.
To address these problems, vias can be offset through individual layers to provide multi-layer interconnections. The pattern of vias through the individual circuit layers resembles a set of steps, which require extra space. The spreading of the vias across the layers limits the circuit density of the carrier and thus the density with which chips can be arranged on the carrier. In addition, the less dense arrangement requires longer signal paths, characterized by higher impedance and longer signal travel time.
Techniques and processes for constructing solid vias within multi-chip carriers have been disclosed in a parent patent application (Ser. No. 07/360,828). While the disclosed methods provide greater via and circuit density within multi-chip carriers, the techniques can become severely degraded from the surface topology of individual circuit layers. Excess and uneven via material, remaining after each fabrication iteration, results in irregular surface topology that makes further alignment and photolithography difficult, if not impossible. Irregular topological features would only worsen as each successive layer is attached to the previous. What is needed is a method of improving the surface topology of integrated circuit surfaces in order to align and stack individual circuit layers accurately. More specifically, what is needed is a method of fabricating a layer of vias with an improved, uniform surface topology, while leaving delicate multi-chip carrier structures intact.